This paper presents the tree structure of the solution set for logic partitioning problem and some matrix inequalities relating to the total amount of pins.
本文给出了逻辑划分问题解集合的树结构以及有关总针数的若干矩阵不等式，建立了一个分枝限界算法。
This paper describes the partitioning of the set pf the Boolean equations generated by the hardware logic translator and the conversion of the subset into cube arrays.
本文阐明将硬件逻辑翻译器产生的布尔方程集合划分成子集后，转换成多维体列阵。
Presents a layout strategy based on partitioning, that can efficiently solve the problem of automatic generation of logic schematics for VLSI.
提出基于划分的逻辑图布图策略，有效解决超大规模集成电路(VL SI)逻辑原理图自动生成中规模与速度的矛盾，给出详细的划分模型。
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